This article discusses the following factors as they relate to valid first conversions: The resulting DAC input is a digital approximation of the sampled input voltage, and is output by the ADC at the end of the conversion. This binary search continues until every bit in the register is tested. The process repeats with the next most significant bit, turning it off if the comparator determines that the DAC output is larger than the analog input, or keeping it on if the output was smaller. After the comparator output has settled, the successive-approximation register turns off the MSB if the DAC output was larger than the analog input, or keeps it on if the output was smaller. To start, the most significant bit (MSB) is on, setting the DAC output voltage to midscale. When the switch opens, the comparator determines whether the analog input, which is now stored on the hold capacitor, is greater than or less than the DAC voltage. The switch closes, connecting the analog input to the SHA, which acquires the input voltage. Because the SAR controls the converter’s operation, successive-approximation converters are often called SAR ADCs.Īfter power-up and initialization, a signal on CONVERT starts the conversion cycle. Successive-approximation ADCs comprise four main subcircuits: the sample-and-hold amplifier (SHA), analog comparator, reference digital-to-analog converter (DAC), and successive-approximation register (SAR).
SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER HOW TO
This article shows how to initialize a successive-approximation ADC to get valid conversions.
Successive-approximation analog-to-digital converters (ADCs) with up to 18-bit resolution and 10-MSPS sample rates meet the demands of many data-acquisition applications, including portable, industrial, medical, and communications. Successive-Approximation ADCs: Ensuring a Valid First Conversion